Designing electronics for reliable high speed signal transmission requires attention be paid to signal trace quality, trace geometries, and impedance matching. This is true for both printed circuit boards as well as integrated circuit (“IC”) packages attached to the printed circuit board (“PCB”). An example of a high speed IC is a Serdes IC, which is a contraction for serialization-deserialization integrated circuit. A Serdes IC typically has multiple transmission and receive channels. In order to minimize noise, common mode voltages, and other non-optimum signal characteristics affecting system performance, the Serdes design uses a differential pair for each transmission and receive channel. The Serdes IC package, therefore, must accommodate at least as many differential pair traces as there are channels and route those channels to leads of the IC where they can be implemented as part of a larger system.
A conventional configuration of high-speed signal traces for differential pairs on an IC package or a PCB comprises an edge-side coupled, configuration in which traces are positioned co-planar and parallel to each other. A typical laminate IC package or PCB has a dielectric constant of approximately 4. This permits relatively close spacing of differential signal pairs in the edge-side coupled configuration. A ceramic IC package is less expensive and has a lower dielectric loss than laminate. Therefore, there are significant benefits to using a ceramic IC package, which has a dielectric constant of between 9.8 and 10. In order to achieve a conventional 50 ohm trace impedance, a ceramic IC package dictates that the differential signal traces have an edge to edge spacing of 300 microns which is wide as compared to the spacing requirements on laminate. Additionally, an edge-side coupled configuration requires a single electrically conductive reference plane. The edge-side coupled differential pairs are positioned on a single layer. An edge-side coupled configuration, therefore, promotes an IC with a large surface area in order to accommodate access to signals on the IC die at a location where they are launched onto the IC package. In other words, the edge-side coupled configuration requires a significant amount of space to properly route the traces to electrically connect all of the transmit and receive channels to the IC package. As one of ordinary skill in the art appreciates, such a large spacing requirement impacts the routing density for a given IC of a given size and greatly increases the cost of the IC.
As electrical systems get smaller, it is desirable to increase the number of channels on an IC die. In an edge-side coupled configuration, in order to increase the number of channels on the IC, an IC die edge must be lengthened to accommodate the additional channels and spacing requirement. In many cases, it is possible to lay out an IC design, so that IC circuitry is positioned in the spaces that might be used for package routing. In a Serdes IC, however, relatively little of the surface area of the IC is used for circuitry. Most of the circuitry is concentrated at one or more channel pads adjacent to the IC die edge. As an example, a transmit signal, a transmit signal complement, a reference potential, and a transmit bias potential are each positioned on a single signal pad unit on the IC. In order to minimize IC area, the four constituent electrical signals may be aligned from the IC die edge towards a center of the IC die. Another channel is similarly aligned and positioned adjacent the first channel pad. The channel-to-channel physical spacing is defined by the amount of space required to route the signal lines while maintaining the appropriate trace impedance. In a conventional edge-side coupled trace configuration in a ceramic package, there should be 300 micron spacing between the signal and signal complement traces. Add this to the amount of space required for channel-to-channel spacing and there is a significant amount of spaces required for trace layout. As the number of channels increase, so does the perimeter of the IC. Under the prior art, incremental increases in the perimeter of the IC die to accommodate an increase in the number of channels causes the surface area of the IC die to increase at a faster rate. The cost of an IC is directly related to the surface area. Under the prior art, therefore, the cost per channel of a Serdes IC increases with an increase in the number of channels on the IC die.
Accordingly, there is a need to maintain the surface area of a Serdes IC while increasing the number of channels the IC can accommodate.